1. Technical Field
The present disclosure relates to sense amplifiers, in particular for reading nonvolatile memory cells, and more particularly to the management of a precharge phase of bitlines of a memory array, before reading a memory cell.
2. Description of the Related Art
Sense amplifiers are conventionally used to sense the state of memory cells and to output a data signal that is a function of that state. FIG. 1 shows schematically the structure of a sense amplifier SA1. The sense amplifier comprises a sensing unit SU, a precharge unit PU, a cascode transistor TC, a biasing unit BU1 and a sense input SI. The cascode transistor TC comprises a gate terminal (G), a drain terminal (D) linked to the sensing unit SU and to the precharge unit PU, and a source terminal (S) connected to the sense input SI. The sense input SI is linked, through a bitline BL, to a memory cell MC to be sensed.
The sensing of the memory cell MC comprises a precharge phase and a read phase. At the beginning of the precharge phase, the precharge unit PU applies a precharge voltage V1 to the drain terminal of the cascode transistor TC and the biasing unit BU1 applies a control voltage Vc to the gate terminal of the cascode transistor, which becomes conducting. The source terminal (S) of the cascode transistor TC supplies a bitline voltage Vbl to the bitline BL through the sense input SI. Voltage Vbl increases and reaches a desired bitline precharge voltage. Then, the precharge voltage V1 ceases to be applied to the cascode transistor, the sensing unit SU is enabled and the read phase starts. The sensing unit SU senses the state of the memory cell MC and outputs a data (D) representing the state of the memory cell.
In order to reduce the read time and minimize stress on the bitlines, the voltage Vbl should be brought as quickly as possible during the precharge phase to the bitline precharge voltage, typically 0.8V or less. Two conventional embodiments of the biasing unit are shown in FIGS. 2A and 3B.
FIG. 2A shows a sense amplifier SA2 comprising a closed loop biasing unit BU2. The biasing unit BU2 comprises a logic gate LG supplying a control voltage Vc to the gate terminal (G) of the cascode transistor TC. The logic gate LG, for example a NOR gate, is connected on one input to the source terminal (S) of the cascode transistor TC and receives on another input a control signal CSG.
At the beginning of the precharge phase, the control signal CSG is set from 1 to 0 and the bitline voltage Vbl is low. The output of the NOR gate goes to 1 which quickly brings the control voltage Vc to a high level, as shown in FIG. 2B, thereby activating the cascode transistor TC. The cascode transistor starts to conduct and the bitline voltage Vbl increases, as also shown in FIG. 2B. When voltage Vbl reaches a trigger point of the logic gate LG, the latter enters an intermediary logic state that is neither 0 nor 1, causing the control voltage Vc to decrease. The decrease of voltage Vc decreases the conductivity of the cascode transistor, thereby slowing down the rate of increase of bitline voltage Vbl until it reaches the desired bitline precharge voltage Vblpre.
FIG. 3A shows a sense amplifier SA3 comprising an open loop biasing unit BU3. The biasing unit BU3 comprises a voltage generator VG having an output linked to the gate terminal of the cascode transistor TC and supplying the control voltage Vc. The voltage generator VG applies voltage Vc to the gate terminal of the cascode transistor TC at the beginning of the precharge phase, as shown in FIG. 3B, thereby setting the cascode transistor TC in the conducting state. The bitline voltage Vbl increases, as shown in FIG. 3B, until it reaches the desired bitline precharge voltage Vblpre. The control voltage is approximately set to a value equal to Vblpre+Vt and therefore is not very high. For this reason, the bitline voltage Vbl has a rising slope RS3 that is less than the rising slope RS2 of the voltage bitline Vbl in FIG. 2B, obtained with the closed loop biasing unit BU2.
In summary, the biasing unit BU2 shown in FIG. 2A allows for a rapid bitline precharge. However, the logic gate LG in the intermediary logic state has a high static current consumption because its pull-up and pull-down transistors are both in the conducting state, while the biasing unit BU3 shown in FIG. 3A has a very low current consumption.
Therefore, it may be desired to provide a sense amplifier having a biasing unit offering a fast precharge time while presenting a low consumption.